10-15K

Analog Layout Engineer 模拟版图工程师

Responsibilities:
1.Convert Logic and Schematic drawings to physical layout in accordance with design rules.
2.Chip planning,chip design and drive layout to DRC and LVS clean.
3.Insure the quality of layout meets our goal for first pass silicon success and achieve time to market objectives.
4.Work with design engineers to resolve any technical issues that will affect layout to insure high quality.
5.Establish and meet project objectives and milestones.
6.Utilize CAD tools for verification to achieve our goal of zero errors.
7.Do Revision Tape outs, which include ECO changes, physical verification, creating mask index paperwork etc.
8.Perform other duties as assigned.
Qualifications:
1.BS degree in Electronics, Drafting or related field.
2.Familiar in CMOS high frequency Analog/Mixed-signal layout Design.
3.Familiar with Analog/Mixed-signal layout methods and matching techniques Knowledge of Cadence Virtuoso Layout Editor and Mentor Calibre physical verification tools is a must.
4.Good working knowledge of Linux is required.